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<div class="textblock"><p>This header file contains identifiers and register-level core functions (or macros) that can be used to access the Xilinx HDMI TX core. </p>
<p>For more information about the operation of this core see the hardware specification and documentation in the higher level driver <a class="el" href="xv__hdmitx_8h.html" title="This is the main header file for Xilinx HDMI TX core. ">xv_hdmitx.h</a> file.</p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who    Date     Changes
</p>
<hr/>
<p>
1.00         10/07/15 Initial release.
1.01  YH     25/07/16 Used UINTPTR instead of u32 for BaseAddress
                      XV_HdmiTx_WriteReg
                      XV_HdmiTx_ReadReg
1.02  YH     14/11/16 Added BRIDGE_YUV420 and BRIDGE_PIXEL mask to PIO Out
1.03  MG     06/03/17 Added XV_HDMITX_AUX_STA_PKT_RDY_MASK
1.04  MMO    03/05/17 Updated the comments for XV_HdmiTx_ReadReg and
                        XV_HdmiTx_WriteReg
1.1   MG     03/05/17 Introduced video mask peripheral
1.2   YH     22/08/17 Added XV_HDMITX_AUD_CTRL_AUDFMT_MASK (Audio Format)
1.3   YH     06/10/17 Added XV_HDMITX_AUD_CTRL_AUDFMT_SHIFT (Audio Format)
1.4   YH     16/01/18 Added PIO_OUT for dedicated reset for each clock domain
                      Added PIO_IN to bridge unlock interrupt
                      Added PIO_OUT to set GCP_AVMUTE
1.5   MMO    11/08/18 Added PIO_IN to bridge overflow and underflow interrupt
      EB     14/08/18 Added XV_HDMITX_HPD_TIMEGRID_OFFSET,
                        XV_HDMITX_TOGGLE_CONF_OFFSET and
                        XV_HDMITX_CONNECT_CONF_OFFSET
</pre> </div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a0711485d228f909cc65b275f866e526c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a0711485d228f909cc65b275f866e526c">XV_HDMITX_HW_H_</a></td></tr>
<tr class="memdesc:a0711485d228f909cc65b275f866e526c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="#a0711485d228f909cc65b275f866e526c">More...</a><br/></td></tr>
<tr class="separator:a0711485d228f909cc65b275f866e526c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3eafe27fd10317ecb42fe689ca593212"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>&#160;&#160;&#160;(0*64)</td></tr>
<tr class="memdesc:a3eafe27fd10317ecb42fe689ca593212"><td class="mdescLeft">&#160;</td><td class="mdescRight">&lt; VER (Version Interface) peripheral register offsets  <a href="#a3eafe27fd10317ecb42fe689ca593212">More...</a><br/></td></tr>
<tr class="separator:a3eafe27fd10317ecb42fe689ca593212"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7f0f14a5d0d925bbff6d86e79678300a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a7f0f14a5d0d925bbff6d86e79678300a">XV_HDMITX_VER_ID_OFFSET</a>&#160;&#160;&#160;((<a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>)+(0*4))</td></tr>
<tr class="memdesc:a7f0f14a5d0d925bbff6d86e79678300a"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Identification * Register offset.  <a href="#a7f0f14a5d0d925bbff6d86e79678300a">More...</a><br/></td></tr>
<tr class="separator:a7f0f14a5d0d925bbff6d86e79678300a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec908667ddf1597c82b2d5c16c21ca87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aec908667ddf1597c82b2d5c16c21ca87">XV_HDMITX_VER_VERSION_OFFSET</a>&#160;&#160;&#160;((<a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>)+(1*4))</td></tr>
<tr class="memdesc:aec908667ddf1597c82b2d5c16c21ca87"><td class="mdescLeft">&#160;</td><td class="mdescRight">VER Version Register * offset.  <a href="#aec908667ddf1597c82b2d5c16c21ca87">More...</a><br/></td></tr>
<tr class="separator:aec908667ddf1597c82b2d5c16c21ca87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f3575afd1ca4f63ffa6c725ff78ee7d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a0f3575afd1ca4f63ffa6c725ff78ee7d">XV_HDMITX_PIO_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(0*4))</td></tr>
<tr class="memdesc:a0f3575afd1ca4f63ffa6c725ff78ee7d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Identification * Register offset.  <a href="#a0f3575afd1ca4f63ffa6c725ff78ee7d">More...</a><br/></td></tr>
<tr class="separator:a0f3575afd1ca4f63ffa6c725ff78ee7d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a09b04c19ceb81d2b9e5064d53e232e17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a09b04c19ceb81d2b9e5064d53e232e17">XV_HDMITX_PIO_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(1*4))</td></tr>
<tr class="memdesc:a09b04c19ceb81d2b9e5064d53e232e17"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register * offset.  <a href="#a09b04c19ceb81d2b9e5064d53e232e17">More...</a><br/></td></tr>
<tr class="separator:a09b04c19ceb81d2b9e5064d53e232e17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8e98120a6a24452d2865d24f740129b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a8e98120a6a24452d2865d24f740129b1">XV_HDMITX_PIO_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(2*4))</td></tr>
<tr class="memdesc:a8e98120a6a24452d2865d24f740129b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Set * offset.  <a href="#a8e98120a6a24452d2865d24f740129b1">More...</a><br/></td></tr>
<tr class="separator:a8e98120a6a24452d2865d24f740129b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad1d5bdab7fa4daf868d93d2edd96f566"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ad1d5bdab7fa4daf868d93d2edd96f566">XV_HDMITX_PIO_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(3*4))</td></tr>
<tr class="memdesc:ad1d5bdab7fa4daf868d93d2edd96f566"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Register Clear * offset.  <a href="#ad1d5bdab7fa4daf868d93d2edd96f566">More...</a><br/></td></tr>
<tr class="separator:ad1d5bdab7fa4daf868d93d2edd96f566"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9374a3f25d4d9c91c02d383d66443b4b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a9374a3f25d4d9c91c02d383d66443b4b">XV_HDMITX_PIO_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(4*4))</td></tr>
<tr class="memdesc:a9374a3f25d4d9c91c02d383d66443b4b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Register * offset.  <a href="#a9374a3f25d4d9c91c02d383d66443b4b">More...</a><br/></td></tr>
<tr class="separator:a9374a3f25d4d9c91c02d383d66443b4b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a73655a77916a05b7d8f82a921f15f7be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a73655a77916a05b7d8f82a921f15f7be">XV_HDMITX_PIO_OUT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(5*4))</td></tr>
<tr class="memdesc:a73655a77916a05b7d8f82a921f15f7be"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register offset.  <a href="#a73655a77916a05b7d8f82a921f15f7be">More...</a><br/></td></tr>
<tr class="separator:a73655a77916a05b7d8f82a921f15f7be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afb3e424d18e1c4b146232b67699824eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#afb3e424d18e1c4b146232b67699824eb">XV_HDMITX_PIO_OUT_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(6*4))</td></tr>
<tr class="memdesc:afb3e424d18e1c4b146232b67699824eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Set * offset.  <a href="#afb3e424d18e1c4b146232b67699824eb">More...</a><br/></td></tr>
<tr class="separator:afb3e424d18e1c4b146232b67699824eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a57cd09ceda16cfc89ad51ab5fd16c625"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a57cd09ceda16cfc89ad51ab5fd16c625">XV_HDMITX_PIO_OUT_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(7*4))</td></tr>
<tr class="memdesc:a57cd09ceda16cfc89ad51ab5fd16c625"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Register Clear * offset.  <a href="#a57cd09ceda16cfc89ad51ab5fd16c625">More...</a><br/></td></tr>
<tr class="separator:a57cd09ceda16cfc89ad51ab5fd16c625"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3aec0a8a571c50309c582ac0a3a66cda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a3aec0a8a571c50309c582ac0a3a66cda">XV_HDMITX_PIO_OUT_MSK_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(8*4))</td></tr>
<tr class="memdesc:a3aec0a8a571c50309c582ac0a3a66cda"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Mask Register * offset.  <a href="#a3aec0a8a571c50309c582ac0a3a66cda">More...</a><br/></td></tr>
<tr class="separator:a3aec0a8a571c50309c582ac0a3a66cda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae1aa781005ce21dab9e7af6e4c091d0e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae1aa781005ce21dab9e7af6e4c091d0e">XV_HDMITX_PIO_IN_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(9*4))</td></tr>
<tr class="memdesc:ae1aa781005ce21dab9e7af6e4c091d0e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Register offset.  <a href="#ae1aa781005ce21dab9e7af6e4c091d0e">More...</a><br/></td></tr>
<tr class="separator:ae1aa781005ce21dab9e7af6e4c091d0e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5393d399e287df6c50b6c32b90b1cf93"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a5393d399e287df6c50b6c32b90b1cf93">XV_HDMITX_PIO_IN_EVT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(10*4))</td></tr>
<tr class="memdesc:a5393d399e287df6c50b6c32b90b1cf93"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Register * offset.  <a href="#a5393d399e287df6c50b6c32b90b1cf93">More...</a><br/></td></tr>
<tr class="separator:a5393d399e287df6c50b6c32b90b1cf93"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a50a497ec4e91768009efd7752e7ed9f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a50a497ec4e91768009efd7752e7ed9f6">XV_HDMITX_PIO_IN_EVT_RE_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(11*4))</td></tr>
<tr class="memdesc:a50a497ec4e91768009efd7752e7ed9f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Rising Edge Register offset.  <a href="#a50a497ec4e91768009efd7752e7ed9f6">More...</a><br/></td></tr>
<tr class="separator:a50a497ec4e91768009efd7752e7ed9f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab26c31b92aedb7564284403ca2db65f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab26c31b92aedb7564284403ca2db65f5">XV_HDMITX_PIO_IN_EVT_FE_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(12*4))</td></tr>
<tr class="memdesc:ab26c31b92aedb7564284403ca2db65f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Event Falling Edge Register offset.  <a href="#ab26c31b92aedb7564284403ca2db65f5">More...</a><br/></td></tr>
<tr class="separator:ab26c31b92aedb7564284403ca2db65f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a156f0cd891a36ae3a64beec049eec7e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a156f0cd891a36ae3a64beec049eec7e2">XV_HDMITX_HPD_TIMEGRID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(13*4))</td></tr>
<tr class="memdesc:a156f0cd891a36ae3a64beec049eec7e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO HPD Config.  <a href="#a156f0cd891a36ae3a64beec049eec7e2">More...</a><br/></td></tr>
<tr class="separator:a156f0cd891a36ae3a64beec049eec7e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6a3dac57dd04dfaa2605bbc65f53755"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae6a3dac57dd04dfaa2605bbc65f53755">XV_HDMITX_TOGGLE_CONF_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(14*4))</td></tr>
<tr class="memdesc:ae6a3dac57dd04dfaa2605bbc65f53755"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO HPD Config.  <a href="#ae6a3dac57dd04dfaa2605bbc65f53755">More...</a><br/></td></tr>
<tr class="separator:ae6a3dac57dd04dfaa2605bbc65f53755"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa822ff727ff8bbf1c83a6fc0dd27d1db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aa822ff727ff8bbf1c83a6fc0dd27d1db">XV_HDMITX_CONNECT_CONF_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(15*4))</td></tr>
<tr class="memdesc:aa822ff727ff8bbf1c83a6fc0dd27d1db"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO HPD Config.  <a href="#aa822ff727ff8bbf1c83a6fc0dd27d1db">More...</a><br/></td></tr>
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<tr class="memitem:a40a412194d70fcbb53cef17eea048fa3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a40a412194d70fcbb53cef17eea048fa3">XV_HDMITX_PIO_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a40a412194d70fcbb53cef17eea048fa3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Run mask.  <a href="#a40a412194d70fcbb53cef17eea048fa3">More...</a><br/></td></tr>
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<tr class="memitem:a912027acfdcf62f09ebcb9c4eafb1a74"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a912027acfdcf62f09ebcb9c4eafb1a74">XV_HDMITX_PIO_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a912027acfdcf62f09ebcb9c4eafb1a74"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Control Interrupt Enable mask.  <a href="#a912027acfdcf62f09ebcb9c4eafb1a74">More...</a><br/></td></tr>
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<tr class="memitem:aa8c178b5851211ca5b20faee275a73f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aa8c178b5851211ca5b20faee275a73f8">XV_HDMITX_PIO_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aa8c178b5851211ca5b20faee275a73f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Status Interrupt mask.  <a href="#aa8c178b5851211ca5b20faee275a73f8">More...</a><br/></td></tr>
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<tr class="memitem:aca60ad2b7145ae20f665c42136e63bb7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aca60ad2b7145ae20f665c42136e63bb7">XV_HDMITX_PIO_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
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<tr class="memitem:a3492813bb70421de0a228014bf8d949b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a3492813bb70421de0a228014bf8d949b">XV_HDMITX_PIO_OUT_RST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a3492813bb70421de0a228014bf8d949b"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Reset mask.  <a href="#a3492813bb70421de0a228014bf8d949b">More...</a><br/></td></tr>
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<tr class="memitem:a8b22105cf60c90514691a778c3652769"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a8b22105cf60c90514691a778c3652769">XV_HDMITX_PIO_OUT_MODE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
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<tr class="memitem:a564d1abff6cb04057811a461cfbcb692"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a564d1abff6cb04057811a461cfbcb692">XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK</a>&#160;&#160;&#160;0x30</td></tr>
<tr class="memdesc:a564d1abff6cb04057811a461cfbcb692"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Depth mask.  <a href="#a564d1abff6cb04057811a461cfbcb692">More...</a><br/></td></tr>
<tr class="separator:a564d1abff6cb04057811a461cfbcb692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92829fb1e590c09d7cb030093ed38ba3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a92829fb1e590c09d7cb030093ed38ba3">XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK</a>&#160;&#160;&#160;0xC0</td></tr>
<tr class="memdesc:a92829fb1e590c09d7cb030093ed38ba3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate mask.  <a href="#a92829fb1e590c09d7cb030093ed38ba3">More...</a><br/></td></tr>
<tr class="separator:a92829fb1e590c09d7cb030093ed38ba3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad69a761dfc73ee26434f08f27c83dcdf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ad69a761dfc73ee26434f08f27c83dcdf">XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK</a>&#160;&#160;&#160;0x300</td></tr>
<tr class="memdesc:ad69a761dfc73ee26434f08f27c83dcdf"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate mask.  <a href="#ad69a761dfc73ee26434f08f27c83dcdf">More...</a><br/></td></tr>
<tr class="separator:ad69a761dfc73ee26434f08f27c83dcdf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a461cc5f1205b18c92863bbd3042540b7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a461cc5f1205b18c92863bbd3042540b7">XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK</a>&#160;&#160;&#160;0xC00</td></tr>
<tr class="memdesc:a461cc5f1205b18c92863bbd3042540b7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space mask.  <a href="#a461cc5f1205b18c92863bbd3042540b7">More...</a><br/></td></tr>
<tr class="separator:a461cc5f1205b18c92863bbd3042540b7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aec658e14a00798e20cec912c330c4d0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aec658e14a00798e20cec912c330c4d0d">XV_HDMITX_PIO_OUT_SCRM_MASK</a>&#160;&#160;&#160;(1&lt;&lt;12)</td></tr>
<tr class="memdesc:aec658e14a00798e20cec912c330c4d0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Scrambler mask.  <a href="#aec658e14a00798e20cec912c330c4d0d">More...</a><br/></td></tr>
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<tr class="memitem:aa3936d875363ae229e89ab0d93005173"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aa3936d875363ae229e89ab0d93005173">XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:aa3936d875363ae229e89ab0d93005173"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Depth shift.  <a href="#aa3936d875363ae229e89ab0d93005173">More...</a><br/></td></tr>
<tr class="separator:aa3936d875363ae229e89ab0d93005173"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad507e1024a352cdf174c99ade627b5fb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ad507e1024a352cdf174c99ade627b5fb">XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ad507e1024a352cdf174c99ade627b5fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Pixel Rate shift.  <a href="#ad507e1024a352cdf174c99ade627b5fb">More...</a><br/></td></tr>
<tr class="separator:ad507e1024a352cdf174c99ade627b5fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae81b504f82f4bb53a7f6340c91b722f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae81b504f82f4bb53a7f6340c91b722f5">XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ae81b504f82f4bb53a7f6340c91b722f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Sample Rate shift.  <a href="#ae81b504f82f4bb53a7f6340c91b722f5">More...</a><br/></td></tr>
<tr class="separator:ae81b504f82f4bb53a7f6340c91b722f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac01a89ba24d5a2044caa1377a5aea7aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ac01a89ba24d5a2044caa1377a5aea7aa">XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT</a>&#160;&#160;&#160;10</td></tr>
<tr class="memdesc:ac01a89ba24d5a2044caa1377a5aea7aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Color Space shift.  <a href="#ac01a89ba24d5a2044caa1377a5aea7aa">More...</a><br/></td></tr>
<tr class="separator:ac01a89ba24d5a2044caa1377a5aea7aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5057e256f62c3af0dc0c4e08a6ebf5b3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a5057e256f62c3af0dc0c4e08a6ebf5b3">XV_HDMITX_PIO_OUT_GCP_CLEARAVMUTE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;28)</td></tr>
<tr class="memdesc:a5057e256f62c3af0dc0c4e08a6ebf5b3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out GCP_CLEARAVMUTE mask.  <a href="#a5057e256f62c3af0dc0c4e08a6ebf5b3">More...</a><br/></td></tr>
<tr class="separator:a5057e256f62c3af0dc0c4e08a6ebf5b3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae631917853f4efc05ec48b91a487e22e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae631917853f4efc05ec48b91a487e22e">XV_HDMITX_PIO_OUT_BRIDGE_YUV420_MASK</a>&#160;&#160;&#160;(1&lt;&lt;29)</td></tr>
<tr class="memdesc:ae631917853f4efc05ec48b91a487e22e"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_YUV420 mask.  <a href="#ae631917853f4efc05ec48b91a487e22e">More...</a><br/></td></tr>
<tr class="separator:ae631917853f4efc05ec48b91a487e22e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a43259fa8be8e6d4990e225e7ef66deb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a43259fa8be8e6d4990e225e7ef66deb6">XV_HDMITX_PIO_OUT_BRIDGE_PIXEL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;30)</td></tr>
<tr class="memdesc:a43259fa8be8e6d4990e225e7ef66deb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out Bridge_Pixel repeat mask.  <a href="#a43259fa8be8e6d4990e225e7ef66deb6">More...</a><br/></td></tr>
<tr class="separator:a43259fa8be8e6d4990e225e7ef66deb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aecae9177f56bf35251db6c967b60c2a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aecae9177f56bf35251db6c967b60c2a3">XV_HDMITX_PIO_OUT_GCP_AVMUTE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;31)</td></tr>
<tr class="memdesc:aecae9177f56bf35251db6c967b60c2a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out GCP_AVMUTE mask.  <a href="#aecae9177f56bf35251db6c967b60c2a3">More...</a><br/></td></tr>
<tr class="separator:aecae9177f56bf35251db6c967b60c2a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aaae3285766545ae8b717a709c376d449"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aaae3285766545ae8b717a709c376d449">XV_HDMITX_PIO_OUT_INT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aaae3285766545ae8b717a709c376d449"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_VRST mask.  <a href="#aaae3285766545ae8b717a709c376d449">More...</a><br/></td></tr>
<tr class="separator:aaae3285766545ae8b717a709c376d449"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a190850cf65d40a36c67965b58ab719a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a190850cf65d40a36c67965b58ab719a7">XV_HDMITX_PIO_OUT_INT_LRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;20)</td></tr>
<tr class="memdesc:a190850cf65d40a36c67965b58ab719a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out INT_LRST mask.  <a href="#a190850cf65d40a36c67965b58ab719a7">More...</a><br/></td></tr>
<tr class="separator:a190850cf65d40a36c67965b58ab719a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a85c45b96a6535758a64f4bbde6736b30"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a85c45b96a6535758a64f4bbde6736b30">XV_HDMITX_PIO_OUT_EXT_VRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;21)</td></tr>
<tr class="memdesc:a85c45b96a6535758a64f4bbde6736b30"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_VRST mask.  <a href="#a85c45b96a6535758a64f4bbde6736b30">More...</a><br/></td></tr>
<tr class="separator:a85c45b96a6535758a64f4bbde6736b30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae6f495059257675ab6aab20debbb29ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae6f495059257675ab6aab20debbb29ae">XV_HDMITX_PIO_OUT_EXT_SYSRST_MASK</a>&#160;&#160;&#160;(1&lt;&lt;22)</td></tr>
<tr class="memdesc:ae6f495059257675ab6aab20debbb29ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO Out EXT_SYSRST mask.  <a href="#ae6f495059257675ab6aab20debbb29ae">More...</a><br/></td></tr>
<tr class="separator:ae6f495059257675ab6aab20debbb29ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af84ed4e0a3e63ee5b5eeb18b5f9172f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#af84ed4e0a3e63ee5b5eeb18b5f9172f6">XV_HDMITX_PIO_IN_LNK_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:af84ed4e0a3e63ee5b5eeb18b5f9172f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In link ready mask.  <a href="#af84ed4e0a3e63ee5b5eeb18b5f9172f6">More...</a><br/></td></tr>
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<tr class="memitem:a8eae374abecb5156f5827c2543467866"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a8eae374abecb5156f5827c2543467866">XV_HDMITX_PIO_IN_VID_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a8eae374abecb5156f5827c2543467866"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In video ready mask.  <a href="#a8eae374abecb5156f5827c2543467866">More...</a><br/></td></tr>
<tr class="separator:a8eae374abecb5156f5827c2543467866"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38b7234925ae25a8a5104c446e2b0c50"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a38b7234925ae25a8a5104c446e2b0c50">XV_HDMITX_PIO_IN_HPD_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a38b7234925ae25a8a5104c446e2b0c50"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In HPD mask.  <a href="#a38b7234925ae25a8a5104c446e2b0c50">More...</a><br/></td></tr>
<tr class="separator:a38b7234925ae25a8a5104c446e2b0c50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5e6881f3d1d651347a8e507c6d708aa6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a5e6881f3d1d651347a8e507c6d708aa6">XV_HDMITX_PIO_IN_VS_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a5e6881f3d1d651347a8e507c6d708aa6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Vsync mask.  <a href="#a5e6881f3d1d651347a8e507c6d708aa6">More...</a><br/></td></tr>
<tr class="separator:a5e6881f3d1d651347a8e507c6d708aa6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afe3ba46026108ca4004a2c1f4e175cda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#afe3ba46026108ca4004a2c1f4e175cda">XV_HDMITX_PIO_IN_PPP_MASK</a>&#160;&#160;&#160;0x07</td></tr>
<tr class="memdesc:afe3ba46026108ca4004a2c1f4e175cda"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Pixel packing phase mask.  <a href="#afe3ba46026108ca4004a2c1f4e175cda">More...</a><br/></td></tr>
<tr class="separator:afe3ba46026108ca4004a2c1f4e175cda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a02fe47969aef0025a0dcde5f67059f4a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a02fe47969aef0025a0dcde5f67059f4a">XV_HDMITX_PIO_IN_HPD_TOGGLE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:a02fe47969aef0025a0dcde5f67059f4a"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In HPD toggle mask.  <a href="#a02fe47969aef0025a0dcde5f67059f4a">More...</a><br/></td></tr>
<tr class="separator:a02fe47969aef0025a0dcde5f67059f4a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a53a26ad8c741bb6defdabaf539c15f76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a53a26ad8c741bb6defdabaf539c15f76">XV_HDMITX_PIO_IN_PPP_SHIFT</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:a53a26ad8c741bb6defdabaf539c15f76"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Pixel packing phase shift.  <a href="#a53a26ad8c741bb6defdabaf539c15f76">More...</a><br/></td></tr>
<tr class="separator:a53a26ad8c741bb6defdabaf539c15f76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af0d1a093d1b0ef6ff6d0c595fbbc689d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#af0d1a093d1b0ef6ff6d0c595fbbc689d">XV_HDMITX_PIO_IN_BRDG_LOCKED_MASK</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:af0d1a093d1b0ef6ff6d0c595fbbc689d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Bridge Locked mask.  <a href="#af0d1a093d1b0ef6ff6d0c595fbbc689d">More...</a><br/></td></tr>
<tr class="separator:af0d1a093d1b0ef6ff6d0c595fbbc689d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a183040712bab60e3b122ced003b6094d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a183040712bab60e3b122ced003b6094d">XV_HDMITX_PIO_IN_BRDG_OVERFLOW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;10)</td></tr>
<tr class="memdesc:a183040712bab60e3b122ced003b6094d"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Bridge Overflow mask.  <a href="#a183040712bab60e3b122ced003b6094d">More...</a><br/></td></tr>
<tr class="separator:a183040712bab60e3b122ced003b6094d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aeeca103fdb0a14d806a07cbbbac3a5a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aeeca103fdb0a14d806a07cbbbac3a5a6">XV_HDMITX_PIO_IN_BRDG_UNDERFLOW_MASK</a>&#160;&#160;&#160;(1&lt;&lt;11)</td></tr>
<tr class="memdesc:aeeca103fdb0a14d806a07cbbbac3a5a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">PIO In Bridge Underflow mask.  <a href="#aeeca103fdb0a14d806a07cbbbac3a5a6">More...</a><br/></td></tr>
<tr class="separator:aeeca103fdb0a14d806a07cbbbac3a5a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4af3a11ac2e2a2190f6e8c39111199d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a4af3a11ac2e2a2190f6e8c39111199d3">XV_HDMITX_DDC_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(0*4))</td></tr>
<tr class="memdesc:a4af3a11ac2e2a2190f6e8c39111199d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Identification * Register offset.  <a href="#a4af3a11ac2e2a2190f6e8c39111199d3">More...</a><br/></td></tr>
<tr class="separator:a4af3a11ac2e2a2190f6e8c39111199d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afaed19df9105685cea7b51363e5aab38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#afaed19df9105685cea7b51363e5aab38">XV_HDMITX_DDC_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(1*4))</td></tr>
<tr class="memdesc:afaed19df9105685cea7b51363e5aab38"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register * offset.  <a href="#afaed19df9105685cea7b51363e5aab38">More...</a><br/></td></tr>
<tr class="separator:afaed19df9105685cea7b51363e5aab38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aab4ea6581cb2fd09a5aabd906da25b17"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aab4ea6581cb2fd09a5aabd906da25b17">XV_HDMITX_DDC_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(2*4))</td></tr>
<tr class="memdesc:aab4ea6581cb2fd09a5aabd906da25b17"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Set * offset.  <a href="#aab4ea6581cb2fd09a5aabd906da25b17">More...</a><br/></td></tr>
<tr class="separator:aab4ea6581cb2fd09a5aabd906da25b17"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0183fc18bbe56540d95fc291e3060c38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a0183fc18bbe56540d95fc291e3060c38">XV_HDMITX_DDC_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(3*4))</td></tr>
<tr class="memdesc:a0183fc18bbe56540d95fc291e3060c38"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Register Clear * offset.  <a href="#a0183fc18bbe56540d95fc291e3060c38">More...</a><br/></td></tr>
<tr class="separator:a0183fc18bbe56540d95fc291e3060c38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add689faff8e7c346c9d8202355678a22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#add689faff8e7c346c9d8202355678a22">XV_HDMITX_DDC_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(4*4))</td></tr>
<tr class="memdesc:add689faff8e7c346c9d8202355678a22"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Register * offset.  <a href="#add689faff8e7c346c9d8202355678a22">More...</a><br/></td></tr>
<tr class="separator:add689faff8e7c346c9d8202355678a22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7356d56189f12a10c6f79a97012e3882"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a7356d56189f12a10c6f79a97012e3882">XV_HDMITX_DDC_CMD_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(5*4))</td></tr>
<tr class="memdesc:a7356d56189f12a10c6f79a97012e3882"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Command Register * offset.  <a href="#a7356d56189f12a10c6f79a97012e3882">More...</a><br/></td></tr>
<tr class="separator:a7356d56189f12a10c6f79a97012e3882"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aafc52187f15507e2b6b6f7438ddb3c8c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aafc52187f15507e2b6b6f7438ddb3c8c">XV_HDMITX_DDC_DAT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(6*4))</td></tr>
<tr class="memdesc:aafc52187f15507e2b6b6f7438ddb3c8c"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Data Register * offset.  <a href="#aafc52187f15507e2b6b6f7438ddb3c8c">More...</a><br/></td></tr>
<tr class="separator:aafc52187f15507e2b6b6f7438ddb3c8c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a25f1a215971c5370677b19e3b9f16bf2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a25f1a215971c5370677b19e3b9f16bf2">XV_HDMITX_DDC_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a25f1a215971c5370677b19e3b9f16bf2"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Run mask.  <a href="#a25f1a215971c5370677b19e3b9f16bf2">More...</a><br/></td></tr>
<tr class="separator:a25f1a215971c5370677b19e3b9f16bf2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b2d0351f601ac8afdc99e651a916111"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a0b2d0351f601ac8afdc99e651a916111">XV_HDMITX_DDC_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a0b2d0351f601ac8afdc99e651a916111"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Interrupt Enable mask.  <a href="#a0b2d0351f601ac8afdc99e651a916111">More...</a><br/></td></tr>
<tr class="separator:a0b2d0351f601ac8afdc99e651a916111"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1e7d988ba6707bb1cd58fa9af9db6ae0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a1e7d988ba6707bb1cd58fa9af9db6ae0">XV_HDMITX_DDC_CTRL_CLK_DIV_MASK</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a1e7d988ba6707bb1cd58fa9af9db6ae0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Control Clock Divider mask.  <a href="#a1e7d988ba6707bb1cd58fa9af9db6ae0">More...</a><br/></td></tr>
<tr class="separator:a1e7d988ba6707bb1cd58fa9af9db6ae0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aed853aca89756ea743e083e7573d1617"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aed853aca89756ea743e083e7573d1617">XV_HDMITX_DDC_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:aed853aca89756ea743e083e7573d1617"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status IRQ mask.  <a href="#aed853aca89756ea743e083e7573d1617">More...</a><br/></td></tr>
<tr class="separator:aed853aca89756ea743e083e7573d1617"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad944d773e9619b1d2076aa5bc0d9f4e2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ad944d773e9619b1d2076aa5bc0d9f4e2">XV_HDMITX_DDC_STA_EVT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ad944d773e9619b1d2076aa5bc0d9f4e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Event mask.  <a href="#ad944d773e9619b1d2076aa5bc0d9f4e2">More...</a><br/></td></tr>
<tr class="separator:ad944d773e9619b1d2076aa5bc0d9f4e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad2f3f71a213bc05457101200b03d2ebe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ad2f3f71a213bc05457101200b03d2ebe">XV_HDMITX_DDC_STA_BUSY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:ad2f3f71a213bc05457101200b03d2ebe"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Busy mask.  <a href="#ad2f3f71a213bc05457101200b03d2ebe">More...</a><br/></td></tr>
<tr class="separator:ad2f3f71a213bc05457101200b03d2ebe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5c2fcc8362b12929e9069f044c452bd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a5c2fcc8362b12929e9069f044c452bd7">XV_HDMITX_DDC_STA_DONE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:a5c2fcc8362b12929e9069f044c452bd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Busy mask.  <a href="#a5c2fcc8362b12929e9069f044c452bd7">More...</a><br/></td></tr>
<tr class="separator:a5c2fcc8362b12929e9069f044c452bd7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab4cc4517f9d2cdacd81718603c6a2308"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab4cc4517f9d2cdacd81718603c6a2308">XV_HDMITX_DDC_STA_TIMEOUT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;4)</td></tr>
<tr class="memdesc:ab4cc4517f9d2cdacd81718603c6a2308"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status Timeout mask.  <a href="#ab4cc4517f9d2cdacd81718603c6a2308">More...</a><br/></td></tr>
<tr class="separator:ab4cc4517f9d2cdacd81718603c6a2308"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af77c4ab50461a2356e62aaa8fa279bab"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#af77c4ab50461a2356e62aaa8fa279bab">XV_HDMITX_DDC_STA_ACK_MASK</a>&#160;&#160;&#160;(1&lt;&lt;5)</td></tr>
<tr class="memdesc:af77c4ab50461a2356e62aaa8fa279bab"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC Status ACK mask.  <a href="#af77c4ab50461a2356e62aaa8fa279bab">More...</a><br/></td></tr>
<tr class="separator:af77c4ab50461a2356e62aaa8fa279bab"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab98e29e866183af70534dbf21deb4963"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab98e29e866183af70534dbf21deb4963">XV_HDMITX_DDC_STA_SCL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;6)</td></tr>
<tr class="memdesc:ab98e29e866183af70534dbf21deb4963"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC State of SCL Input mask.  <a href="#ab98e29e866183af70534dbf21deb4963">More...</a><br/></td></tr>
<tr class="separator:ab98e29e866183af70534dbf21deb4963"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae486edb257d9135145951631a6b4b110"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae486edb257d9135145951631a6b4b110">XV_HDMITX_DDC_STA_SDA_MASK</a>&#160;&#160;&#160;(1&lt;&lt;7)</td></tr>
<tr class="memdesc:ae486edb257d9135145951631a6b4b110"><td class="mdescLeft">&#160;</td><td class="mdescRight">DDC State of SDA Input mask.  <a href="#ae486edb257d9135145951631a6b4b110">More...</a><br/></td></tr>
<tr class="separator:ae486edb257d9135145951631a6b4b110"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a108fb0a980dd01604d286d675f001a21"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a108fb0a980dd01604d286d675f001a21">XV_HDMITX_DDC_STA_CMD_FULL</a>&#160;&#160;&#160;(1&lt;&lt;8)</td></tr>
<tr class="memdesc:a108fb0a980dd01604d286d675f001a21"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command fifo full.  <a href="#a108fb0a980dd01604d286d675f001a21">More...</a><br/></td></tr>
<tr class="separator:a108fb0a980dd01604d286d675f001a21"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab39f53e62517e7756ccaae1972635e71"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab39f53e62517e7756ccaae1972635e71">XV_HDMITX_DDC_STA_DAT_EMPTY</a>&#160;&#160;&#160;(1&lt;&lt;9)</td></tr>
<tr class="memdesc:ab39f53e62517e7756ccaae1972635e71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data fifo empty.  <a href="#ab39f53e62517e7756ccaae1972635e71">More...</a><br/></td></tr>
<tr class="separator:ab39f53e62517e7756ccaae1972635e71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab64afd200f27ec3c82835a75eca6f61c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab64afd200f27ec3c82835a75eca6f61c">XV_HDMITX_DDC_STA_CMD_WRDS_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:ab64afd200f27ec3c82835a75eca6f61c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command fifo words mask.  <a href="#ab64afd200f27ec3c82835a75eca6f61c">More...</a><br/></td></tr>
<tr class="separator:ab64afd200f27ec3c82835a75eca6f61c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a14e07ba89f7f88769f399f1e7fa640dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a14e07ba89f7f88769f399f1e7fa640dc">XV_HDMITX_DDC_STA_CMD_WRDS_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:a14e07ba89f7f88769f399f1e7fa640dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Command fifo words shift.  <a href="#a14e07ba89f7f88769f399f1e7fa640dc">More...</a><br/></td></tr>
<tr class="separator:a14e07ba89f7f88769f399f1e7fa640dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a453c5f4507cb2b4d399eb0f778ccf934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a453c5f4507cb2b4d399eb0f778ccf934">XV_HDMITX_DDC_STA_DAT_WRDS_MASK</a>&#160;&#160;&#160;0xFF</td></tr>
<tr class="memdesc:a453c5f4507cb2b4d399eb0f778ccf934"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data fifo words mask.  <a href="#a453c5f4507cb2b4d399eb0f778ccf934">More...</a><br/></td></tr>
<tr class="separator:a453c5f4507cb2b4d399eb0f778ccf934"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a59938ef823d937157bdbe0ffd06ed0d8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a59938ef823d937157bdbe0ffd06ed0d8">XV_HDMITX_DDC_STA_DAT_WRDS_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:a59938ef823d937157bdbe0ffd06ed0d8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data fifo words shift.  <a href="#a59938ef823d937157bdbe0ffd06ed0d8">More...</a><br/></td></tr>
<tr class="separator:a59938ef823d937157bdbe0ffd06ed0d8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab6901facaddc25fe1f07d0eee6e65908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab6901facaddc25fe1f07d0eee6e65908">XV_HDMITX_DDC_CMD_STR_TOKEN</a>&#160;&#160;&#160;(0x100)</td></tr>
<tr class="memdesc:ab6901facaddc25fe1f07d0eee6e65908"><td class="mdescLeft">&#160;</td><td class="mdescRight">Start token.  <a href="#ab6901facaddc25fe1f07d0eee6e65908">More...</a><br/></td></tr>
<tr class="separator:ab6901facaddc25fe1f07d0eee6e65908"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a17aefbf8e9a56021a1fa7321fca45995"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a17aefbf8e9a56021a1fa7321fca45995">XV_HDMITX_DDC_CMD_STP_TOKEN</a>&#160;&#160;&#160;(0x101)</td></tr>
<tr class="memdesc:a17aefbf8e9a56021a1fa7321fca45995"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop token.  <a href="#a17aefbf8e9a56021a1fa7321fca45995">More...</a><br/></td></tr>
<tr class="separator:a17aefbf8e9a56021a1fa7321fca45995"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77fe4475732ac1844f33515e64590bd0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a77fe4475732ac1844f33515e64590bd0">XV_HDMITX_DDC_CMD_RD_TOKEN</a>&#160;&#160;&#160;(0x102)</td></tr>
<tr class="memdesc:a77fe4475732ac1844f33515e64590bd0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read token.  <a href="#a77fe4475732ac1844f33515e64590bd0">More...</a><br/></td></tr>
<tr class="separator:a77fe4475732ac1844f33515e64590bd0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0a3e0ff5b586f637f7ce58e37e76a0d4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a0a3e0ff5b586f637f7ce58e37e76a0d4">XV_HDMITX_DDC_CMD_WR_TOKEN</a>&#160;&#160;&#160;(0x103)</td></tr>
<tr class="memdesc:a0a3e0ff5b586f637f7ce58e37e76a0d4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write token.  <a href="#a0a3e0ff5b586f637f7ce58e37e76a0d4">More...</a><br/></td></tr>
<tr class="separator:a0a3e0ff5b586f637f7ce58e37e76a0d4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5b8e97815f844573c8549f0b9f8c805c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a5b8e97815f844573c8549f0b9f8c805c">XV_HDMITX_AUX_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(0*4))</td></tr>
<tr class="memdesc:a5b8e97815f844573c8549f0b9f8c805c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Identification * Register offset.  <a href="#a5b8e97815f844573c8549f0b9f8c805c">More...</a><br/></td></tr>
<tr class="separator:a5b8e97815f844573c8549f0b9f8c805c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a650c485d8b048a53058d7a55953db647"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a650c485d8b048a53058d7a55953db647">XV_HDMITX_AUX_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(1*4))</td></tr>
<tr class="memdesc:a650c485d8b048a53058d7a55953db647"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register * offset.  <a href="#a650c485d8b048a53058d7a55953db647">More...</a><br/></td></tr>
<tr class="separator:a650c485d8b048a53058d7a55953db647"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa9117e3cd8d01675a6a9db523a49807e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aa9117e3cd8d01675a6a9db523a49807e">XV_HDMITX_AUX_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(2*4))</td></tr>
<tr class="memdesc:aa9117e3cd8d01675a6a9db523a49807e"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Set * offset.  <a href="#aa9117e3cd8d01675a6a9db523a49807e">More...</a><br/></td></tr>
<tr class="separator:aa9117e3cd8d01675a6a9db523a49807e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a2f87dd0bb31f82655eabba7db6189540"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a2f87dd0bb31f82655eabba7db6189540">XV_HDMITX_AUX_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(3*4))</td></tr>
<tr class="memdesc:a2f87dd0bb31f82655eabba7db6189540"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Register Clear * offset.  <a href="#a2f87dd0bb31f82655eabba7db6189540">More...</a><br/></td></tr>
<tr class="separator:a2f87dd0bb31f82655eabba7db6189540"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aadeed071f9ae80ff300b531ea298f42a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aadeed071f9ae80ff300b531ea298f42a">XV_HDMITX_AUX_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(4*4))</td></tr>
<tr class="memdesc:aadeed071f9ae80ff300b531ea298f42a"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Register * offset.  <a href="#aadeed071f9ae80ff300b531ea298f42a">More...</a><br/></td></tr>
<tr class="separator:aadeed071f9ae80ff300b531ea298f42a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab4ffb246932642063518c85c719350a0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab4ffb246932642063518c85c719350a0">XV_HDMITX_AUX_DAT_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(5*4))</td></tr>
<tr class="memdesc:ab4ffb246932642063518c85c719350a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Data Register * offset.  <a href="#ab4ffb246932642063518c85c719350a0">More...</a><br/></td></tr>
<tr class="separator:ab4ffb246932642063518c85c719350a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a586d49d608b7effcbd9176c782ca59da"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a586d49d608b7effcbd9176c782ca59da">XV_HDMITX_AUX_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a586d49d608b7effcbd9176c782ca59da"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Run mask.  <a href="#a586d49d608b7effcbd9176c782ca59da">More...</a><br/></td></tr>
<tr class="separator:a586d49d608b7effcbd9176c782ca59da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a060b91563a63af214d8ca983278d38eb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a060b91563a63af214d8ca983278d38eb">XV_HDMITX_AUX_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a060b91563a63af214d8ca983278d38eb"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Control Interrupt Enable mask.  <a href="#a060b91563a63af214d8ca983278d38eb">More...</a><br/></td></tr>
<tr class="separator:a060b91563a63af214d8ca983278d38eb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5664a354bf22aa9e19d950a18c9598f4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a5664a354bf22aa9e19d950a18c9598f4">XV_HDMITX_AUX_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a5664a354bf22aa9e19d950a18c9598f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Interrupt mask.  <a href="#a5664a354bf22aa9e19d950a18c9598f4">More...</a><br/></td></tr>
<tr class="separator:a5664a354bf22aa9e19d950a18c9598f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4ba5033c98cfedf815f51ea6c76cb0ec"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a4ba5033c98cfedf815f51ea6c76cb0ec">XV_HDMITX_AUX_STA_FIFO_EMT_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:a4ba5033c98cfedf815f51ea6c76cb0ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Empty mask.  <a href="#a4ba5033c98cfedf815f51ea6c76cb0ec">More...</a><br/></td></tr>
<tr class="separator:a4ba5033c98cfedf815f51ea6c76cb0ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a471c6374f04e71189d48849b294155de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a471c6374f04e71189d48849b294155de">XV_HDMITX_AUX_STA_FIFO_FUL_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:a471c6374f04e71189d48849b294155de"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Full mask.  <a href="#a471c6374f04e71189d48849b294155de">More...</a><br/></td></tr>
<tr class="separator:a471c6374f04e71189d48849b294155de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae8dd52aee290be2984731085f7668e44"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae8dd52aee290be2984731085f7668e44">XV_HDMITX_AUX_STA_PKT_RDY_MASK</a>&#160;&#160;&#160;(1&lt;&lt;3)</td></tr>
<tr class="memdesc:ae8dd52aee290be2984731085f7668e44"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status FIFO Ready mask.  <a href="#ae8dd52aee290be2984731085f7668e44">More...</a><br/></td></tr>
<tr class="separator:ae8dd52aee290be2984731085f7668e44"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a92d6d522c60806a380ed5a6aee2c620c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a92d6d522c60806a380ed5a6aee2c620c">XV_HDMITX_AUX_STA_FREE_PKTS_MASK</a>&#160;&#160;&#160;0x0F</td></tr>
<tr class="memdesc:a92d6d522c60806a380ed5a6aee2c620c"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Free Packets mask.  <a href="#a92d6d522c60806a380ed5a6aee2c620c">More...</a><br/></td></tr>
<tr class="separator:a92d6d522c60806a380ed5a6aee2c620c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc1a9c1d2d63c4849f8fc776838f01cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#adc1a9c1d2d63c4849f8fc776838f01cc">XV_HDMITX_AUX_STA_FREE_PKTS_SHIFT</a>&#160;&#160;&#160;15</td></tr>
<tr class="memdesc:adc1a9c1d2d63c4849f8fc776838f01cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUX Status Free Packets shift.  <a href="#adc1a9c1d2d63c4849f8fc776838f01cc">More...</a><br/></td></tr>
<tr class="separator:adc1a9c1d2d63c4849f8fc776838f01cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa3e1bf1acca1da7e3668b1664ee82fd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aa3e1bf1acca1da7e3668b1664ee82fd3">XV_HDMITX_AUD_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(0*4))</td></tr>
<tr class="memdesc:aa3e1bf1acca1da7e3668b1664ee82fd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Identification * Register offset.  <a href="#aa3e1bf1acca1da7e3668b1664ee82fd3">More...</a><br/></td></tr>
<tr class="separator:aa3e1bf1acca1da7e3668b1664ee82fd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1f37ae939243ded094b88763c8fbcc76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a1f37ae939243ded094b88763c8fbcc76">XV_HDMITX_AUD_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(1*4))</td></tr>
<tr class="memdesc:a1f37ae939243ded094b88763c8fbcc76"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register * offset.  <a href="#a1f37ae939243ded094b88763c8fbcc76">More...</a><br/></td></tr>
<tr class="separator:a1f37ae939243ded094b88763c8fbcc76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0657ebf695c90d411c0ecd63aed71d96"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a0657ebf695c90d411c0ecd63aed71d96">XV_HDMITX_AUD_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(2*4))</td></tr>
<tr class="memdesc:a0657ebf695c90d411c0ecd63aed71d96"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Set * offset.  <a href="#a0657ebf695c90d411c0ecd63aed71d96">More...</a><br/></td></tr>
<tr class="separator:a0657ebf695c90d411c0ecd63aed71d96"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a487977b6c692a3cabd9708d199cc6fde"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a487977b6c692a3cabd9708d199cc6fde">XV_HDMITX_AUD_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(3*4))</td></tr>
<tr class="memdesc:a487977b6c692a3cabd9708d199cc6fde"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Register Clear * offset.  <a href="#a487977b6c692a3cabd9708d199cc6fde">More...</a><br/></td></tr>
<tr class="separator:a487977b6c692a3cabd9708d199cc6fde"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7caf30398bed7b2964861a29271c0bd6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a7caf30398bed7b2964861a29271c0bd6">XV_HDMITX_AUD_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(4*4))</td></tr>
<tr class="memdesc:a7caf30398bed7b2964861a29271c0bd6"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Register * offset.  <a href="#a7caf30398bed7b2964861a29271c0bd6">More...</a><br/></td></tr>
<tr class="separator:a7caf30398bed7b2964861a29271c0bd6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a30dbe14665ee4c6b2ef5188837430071"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a30dbe14665ee4c6b2ef5188837430071">XV_HDMITX_AUD_ACR_CTS_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(5*4))</td></tr>
<tr class="memdesc:a30dbe14665ee4c6b2ef5188837430071"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Clock Regeneration CTS * Register offset.  <a href="#a30dbe14665ee4c6b2ef5188837430071">More...</a><br/></td></tr>
<tr class="separator:a30dbe14665ee4c6b2ef5188837430071"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a702529bf17d853efb695aef1898fba3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a702529bf17d853efb695aef1898fba3b">XV_HDMITX_AUD_ACR_N_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(6*4))</td></tr>
<tr class="memdesc:a702529bf17d853efb695aef1898fba3b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Clock Regeneration N * Register offset.  <a href="#a702529bf17d853efb695aef1898fba3b">More...</a><br/></td></tr>
<tr class="separator:a702529bf17d853efb695aef1898fba3b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a72bdef52359446483eab0a4b6886ba34"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a72bdef52359446483eab0a4b6886ba34">XV_HDMITX_AUD_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a72bdef52359446483eab0a4b6886ba34"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Run mask.  <a href="#a72bdef52359446483eab0a4b6886ba34">More...</a><br/></td></tr>
<tr class="separator:a72bdef52359446483eab0a4b6886ba34"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab6d28afc44db8a26bcd45f828afc5d01"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab6d28afc44db8a26bcd45f828afc5d01">XV_HDMITX_AUD_CTRL_IE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;1)</td></tr>
<tr class="memdesc:ab6d28afc44db8a26bcd45f828afc5d01"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control Interrupt Enable mask.  <a href="#ab6d28afc44db8a26bcd45f828afc5d01">More...</a><br/></td></tr>
<tr class="separator:ab6d28afc44db8a26bcd45f828afc5d01"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a28f589dcdb02f0836911bc48271fca9b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a28f589dcdb02f0836911bc48271fca9b">XV_HDMITX_AUD_CTRL_CH_MASK</a>&#160;&#160;&#160;0x1F</td></tr>
<tr class="memdesc:a28f589dcdb02f0836911bc48271fca9b"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control channels mask.  <a href="#a28f589dcdb02f0836911bc48271fca9b">More...</a><br/></td></tr>
<tr class="separator:a28f589dcdb02f0836911bc48271fca9b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a224d3ce0b2fa5396ac35464ab51e18c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a224d3ce0b2fa5396ac35464ab51e18c0">XV_HDMITX_AUD_CTRL_CH_SHIFT</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:a224d3ce0b2fa5396ac35464ab51e18c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control channels shift.  <a href="#a224d3ce0b2fa5396ac35464ab51e18c0">More...</a><br/></td></tr>
<tr class="separator:a224d3ce0b2fa5396ac35464ab51e18c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a78026a4105a831d8d1e2788c1d6ba913"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a78026a4105a831d8d1e2788c1d6ba913">XV_HDMITX_AUD_CTRL_AUDFMT_MASK</a>&#160;&#160;&#160;0x7</td></tr>
<tr class="memdesc:a78026a4105a831d8d1e2788c1d6ba913"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control AUD Format mask.  <a href="#a78026a4105a831d8d1e2788c1d6ba913">More...</a><br/></td></tr>
<tr class="separator:a78026a4105a831d8d1e2788c1d6ba913"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0507ddc2e25096e01a650cf41849e35f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a0507ddc2e25096e01a650cf41849e35f">XV_HDMITX_AUD_CTRL_AUDFMT_SHIFT</a>&#160;&#160;&#160;9</td></tr>
<tr class="memdesc:a0507ddc2e25096e01a650cf41849e35f"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Control AUD Format shift.  <a href="#a0507ddc2e25096e01a650cf41849e35f">More...</a><br/></td></tr>
<tr class="separator:a0507ddc2e25096e01a650cf41849e35f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a26011fe634f2296a975829bae26517fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a26011fe634f2296a975829bae26517fe">XV_HDMITX_AUD_STA_IRQ_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a26011fe634f2296a975829bae26517fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">AUD Status Interrupt mask.  <a href="#a26011fe634f2296a975829bae26517fe">More...</a><br/></td></tr>
<tr class="separator:a26011fe634f2296a975829bae26517fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a420855708f2f362229d89e1bac673151"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a420855708f2f362229d89e1bac673151">XV_HDMITX_MASK_ID_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(0*4))</td></tr>
<tr class="memdesc:a420855708f2f362229d89e1bac673151"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Identification * Register offset.  <a href="#a420855708f2f362229d89e1bac673151">More...</a><br/></td></tr>
<tr class="separator:a420855708f2f362229d89e1bac673151"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa07be6429aa3de9196a5772fb5fb9df1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aa07be6429aa3de9196a5772fb5fb9df1">XV_HDMITX_MASK_CTRL_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(1*4))</td></tr>
<tr class="memdesc:aa07be6429aa3de9196a5772fb5fb9df1"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Register * offset.  <a href="#aa07be6429aa3de9196a5772fb5fb9df1">More...</a><br/></td></tr>
<tr class="separator:aa07be6429aa3de9196a5772fb5fb9df1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae10fec02c7d56b2f48deee7af38a7b8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ae10fec02c7d56b2f48deee7af38a7b8e">XV_HDMITX_MASK_CTRL_SET_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(2*4))</td></tr>
<tr class="memdesc:ae10fec02c7d56b2f48deee7af38a7b8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Register Set * offset.  <a href="#ae10fec02c7d56b2f48deee7af38a7b8e">More...</a><br/></td></tr>
<tr class="separator:ae10fec02c7d56b2f48deee7af38a7b8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3639d48e4561aad19842fd0d94a845a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a3639d48e4561aad19842fd0d94a845a2">XV_HDMITX_MASK_CTRL_CLR_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(3*4))</td></tr>
<tr class="memdesc:a3639d48e4561aad19842fd0d94a845a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Register Clear * offset.  <a href="#a3639d48e4561aad19842fd0d94a845a2">More...</a><br/></td></tr>
<tr class="separator:a3639d48e4561aad19842fd0d94a845a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aab51c879f7c90771a1d8e0ad70a4c012"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aab51c879f7c90771a1d8e0ad70a4c012">XV_HDMITX_MASK_STA_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(4*4))</td></tr>
<tr class="memdesc:aab51c879f7c90771a1d8e0ad70a4c012"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Status Register * offset.  <a href="#aab51c879f7c90771a1d8e0ad70a4c012">More...</a><br/></td></tr>
<tr class="separator:aab51c879f7c90771a1d8e0ad70a4c012"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a348a93aa41e2334b3daa3cdd15e4b8a7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a348a93aa41e2334b3daa3cdd15e4b8a7">XV_HDMITX_MASK_RED_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(5*4))</td></tr>
<tr class="memdesc:a348a93aa41e2334b3daa3cdd15e4b8a7"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Red Component Register * offset.  <a href="#a348a93aa41e2334b3daa3cdd15e4b8a7">More...</a><br/></td></tr>
<tr class="separator:a348a93aa41e2334b3daa3cdd15e4b8a7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aca10d7d68e20ce01b1cf316e595f36aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#aca10d7d68e20ce01b1cf316e595f36aa">XV_HDMITX_MASK_GREEN_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(6*4))</td></tr>
<tr class="memdesc:aca10d7d68e20ce01b1cf316e595f36aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Green Component Register * offset.  <a href="#aca10d7d68e20ce01b1cf316e595f36aa">More...</a><br/></td></tr>
<tr class="separator:aca10d7d68e20ce01b1cf316e595f36aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9647e1e833bcf466af722bb35001ab8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a9647e1e833bcf466af722bb35001ab8e">XV_HDMITX_MASK_BLUE_OFFSET</a>&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(7*4))</td></tr>
<tr class="memdesc:a9647e1e833bcf466af722bb35001ab8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Blue Component Register * offset.  <a href="#a9647e1e833bcf466af722bb35001ab8e">More...</a><br/></td></tr>
<tr class="separator:a9647e1e833bcf466af722bb35001ab8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a2e6183da180f5788efe86b724434b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a4a2e6183da180f5788efe86b724434b8">XV_HDMITX_MASK_CTRL_RUN_MASK</a>&#160;&#160;&#160;(1&lt;&lt;0)</td></tr>
<tr class="memdesc:a4a2e6183da180f5788efe86b724434b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Run mask.  <a href="#a4a2e6183da180f5788efe86b724434b8">More...</a><br/></td></tr>
<tr class="separator:a4a2e6183da180f5788efe86b724434b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad38ac97d5502d061626fe17deb93b658"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ad38ac97d5502d061626fe17deb93b658">XV_HDMITX_MASK_CTRL_NOISE_MASK</a>&#160;&#160;&#160;(1&lt;&lt;2)</td></tr>
<tr class="memdesc:ad38ac97d5502d061626fe17deb93b658"><td class="mdescLeft">&#160;</td><td class="mdescRight">MASK Control Noise.  <a href="#ad38ac97d5502d061626fe17deb93b658">More...</a><br/></td></tr>
<tr class="separator:ad38ac97d5502d061626fe17deb93b658"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab077de545e32c541e6e01a9d78fdade2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#ab077de545e32c541e6e01a9d78fdade2">XV_HDMITX_SHIFT_16</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ab077de545e32c541e6e01a9d78fdade2"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 shift value  <a href="#ab077de545e32c541e6e01a9d78fdade2">More...</a><br/></td></tr>
<tr class="separator:ab077de545e32c541e6e01a9d78fdade2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74530507b4700c300feb4eceed05668f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a74530507b4700c300feb4eceed05668f">XV_HDMITX_MASK_16</a>&#160;&#160;&#160;0xFFFF</td></tr>
<tr class="memdesc:a74530507b4700c300feb4eceed05668f"><td class="mdescLeft">&#160;</td><td class="mdescRight">16 bit mask value  <a href="#a74530507b4700c300feb4eceed05668f">More...</a><br/></td></tr>
<tr class="separator:a74530507b4700c300feb4eceed05668f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5131cd2488ca4a797d71849293cc1109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a5131cd2488ca4a797d71849293cc1109">XV_HDMITX_PIO_ID</a>&#160;&#160;&#160;0x2200</td></tr>
<tr class="memdesc:a5131cd2488ca4a797d71849293cc1109"><td class="mdescLeft">&#160;</td><td class="mdescRight">TX's PIO ID.  <a href="#a5131cd2488ca4a797d71849293cc1109">More...</a><br/></td></tr>
<tr class="separator:a5131cd2488ca4a797d71849293cc1109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a90f7af607960cdf44deb2b43aab27254"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a90f7af607960cdf44deb2b43aab27254">XV_HdmiTx_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:a90f7af607960cdf44deb2b43aab27254"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input Operations.  <a href="#a90f7af607960cdf44deb2b43aab27254">More...</a><br/></td></tr>
<tr class="separator:a90f7af607960cdf44deb2b43aab27254"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6038ccff274de8b99efc34332d0c41d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a6038ccff274de8b99efc34332d0c41d9">XV_HdmiTx_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:a6038ccff274de8b99efc34332d0c41d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output Operations.  <a href="#a6038ccff274de8b99efc34332d0c41d9">More...</a><br/></td></tr>
<tr class="separator:a6038ccff274de8b99efc34332d0c41d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a41b837de9bdbba60a15baa46362dd851"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a41b837de9bdbba60a15baa46362dd851">XV_HdmiTx_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a90f7af607960cdf44deb2b43aab27254">XV_HdmiTx_In32</a>((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:a41b837de9bdbba60a15baa46362dd851"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a HDMI TX register.  <a href="#a41b837de9bdbba60a15baa46362dd851">More...</a><br/></td></tr>
<tr class="separator:a41b837de9bdbba60a15baa46362dd851"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3b74e3c052543284012c23ec717af9d1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="xv__hdmitx__hw_8h.html#a3b74e3c052543284012c23ec717af9d1">XV_HdmiTx_WriteReg</a>(BaseAddress, RegOffset, Data)&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a6038ccff274de8b99efc34332d0c41d9">XV_HdmiTx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:a3b74e3c052543284012c23ec717af9d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value to a HDMI TX register.  <a href="#a3b74e3c052543284012c23ec717af9d1">More...</a><br/></td></tr>
<tr class="separator:a3b74e3c052543284012c23ec717af9d1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a30dbe14665ee4c6b2ef5188837430071"></a>
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          <td class="memname">#define XV_HDMITX_AUD_ACR_CTS_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(5*4))</td>
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<p>AUD Clock Regeneration CTS * Register offset. </p>

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<a class="anchor" id="a702529bf17d853efb695aef1898fba3b"></a>
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          <td class="memname">#define XV_HDMITX_AUD_ACR_N_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(6*4))</td>
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<p>AUD Clock Regeneration N * Register offset. </p>

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</div>
<a class="anchor" id="a78026a4105a831d8d1e2788c1d6ba913"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_AUDFMT_MASK&#160;&#160;&#160;0x7</td>
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<p>AUD Control AUD Format mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a1969dd5561dba784fdb82a4b8e634256">XV_HdmiTx_GetAudioFormat()</a>, and <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>.</p>

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</div>
<a class="anchor" id="a0507ddc2e25096e01a650cf41849e35f"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_AUDFMT_SHIFT&#160;&#160;&#160;9</td>
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<p>AUD Control AUD Format shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a1969dd5561dba784fdb82a4b8e634256">XV_HdmiTx_GetAudioFormat()</a>, and <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>.</p>

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</div>
<a class="anchor" id="a28f589dcdb02f0836911bc48271fca9b"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_CH_MASK&#160;&#160;&#160;0x1F</td>
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<p>AUD Control channels mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>.</p>

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</div>
<a class="anchor" id="a224d3ce0b2fa5396ac35464ab51e18c0"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_CH_SHIFT&#160;&#160;&#160;4</td>
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<p>AUD Control channels shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>.</p>

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</div>
<a class="anchor" id="a487977b6c692a3cabd9708d199cc6fde"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(3*4))</td>
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<p>AUD Control Register Clear * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>, and <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>.</p>

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</div>
<a class="anchor" id="ab6d28afc44db8a26bcd45f828afc5d01"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
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<p>AUD Control Interrupt Enable mask. </p>

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<a class="anchor" id="a1f37ae939243ded094b88763c8fbcc76"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(1*4))</td>
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<p>AUD Control Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a1969dd5561dba784fdb82a4b8e634256">XV_HdmiTx_GetAudioFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>, and <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>.</p>

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<a class="anchor" id="a72bdef52359446483eab0a4b6886ba34"></a>
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          <td class="memname">#define XV_HDMITX_AUD_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
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<p>AUD Control Run mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>, and <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="a0657ebf695c90d411c0ecd63aed71d96"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Control Register Set * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>, and <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="aa3e1bf1acca1da7e3668b1664ee82fd3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a26011fe634f2296a975829bae26517fe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Interrupt mask. </p>

</div>
</div>
<a class="anchor" id="a7caf30398bed7b2964861a29271c0bd6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUD_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUD_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUD Status Register * offset. </p>

</div>
</div>
<a class="anchor" id="a2f87dd0bb31f82655eabba7db6189540"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a060b91563a63af214d8ca983278d38eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a650c485d8b048a53058d7a55953db647"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register * offset. </p>

</div>
</div>
<a class="anchor" id="a586d49d608b7effcbd9176c782ca59da"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Run mask. </p>

</div>
</div>
<a class="anchor" id="aa9117e3cd8d01675a6a9db523a49807e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="ab4ffb246932642063518c85c719350a0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_DAT_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Data Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#ae75f2ab194a44b9f67b7fa9d4545cb57">XV_HdmiTx_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="a5b8e97815f844573c8549f0b9f8c805c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a4ba5033c98cfedf815f51ea6c76cb0ec"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FIFO_EMT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Empty mask. </p>

</div>
</div>
<a class="anchor" id="a471c6374f04e71189d48849b294155de"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FIFO_FUL_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Full mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#ae75f2ab194a44b9f67b7fa9d4545cb57">XV_HdmiTx_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="a92d6d522c60806a380ed5a6aee2c620c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FREE_PKTS_MASK&#160;&#160;&#160;0x0F</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Free Packets mask. </p>

</div>
</div>
<a class="anchor" id="adc1a9c1d2d63c4849f8fc776838f01cc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_FREE_PKTS_SHIFT&#160;&#160;&#160;15</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Free Packets shift. </p>

</div>
</div>
<a class="anchor" id="a5664a354bf22aa9e19d950a18c9598f4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Interrupt mask. </p>

</div>
</div>
<a class="anchor" id="aadeed071f9ae80ff300b531ea298f42a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_AUX_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#ae75f2ab194a44b9f67b7fa9d4545cb57">XV_HdmiTx_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="ae8dd52aee290be2984731085f7668e44"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_AUX_STA_PKT_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>AUX Status FIFO Ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#ae75f2ab194a44b9f67b7fa9d4545cb57">XV_HdmiTx_AuxSend()</a>.</p>

</div>
</div>
<a class="anchor" id="aa822ff727ff8bbf1c83a6fc0dd27d1db"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_CONNECT_CONF_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(15*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO HPD Config. </p>
<ul>
<li>Register offset </li>
</ul>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a7356d56189f12a10c6f79a97012e3882"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Command Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>.</p>

</div>
</div>
<a class="anchor" id="a77fe4475732ac1844f33515e64590bd0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_RD_TOKEN&#160;&#160;&#160;(0x102)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Read token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>.</p>

</div>
</div>
<a class="anchor" id="a17aefbf8e9a56021a1fa7321fca45995"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_STP_TOKEN&#160;&#160;&#160;(0x101)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Stop token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>, and <a class="el" href="xv__hdmitx_8h.html#a852ea29dc77f7bff5509cbf7fe935ede">XV_HdmiTx_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="ab6901facaddc25fe1f07d0eee6e65908"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_STR_TOKEN&#160;&#160;&#160;(0x100)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Start token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>, and <a class="el" href="xv__hdmitx_8h.html#a852ea29dc77f7bff5509cbf7fe935ede">XV_HdmiTx_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="a0a3e0ff5b586f637f7ce58e37e76a0d4"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CMD_WR_TOKEN&#160;&#160;&#160;(0x103)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Write token. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a09f62badd2afc029e5e4967644a37e5f">XV_HdmiTx_DdcRead()</a>, and <a class="el" href="xv__hdmitx_8h.html#a852ea29dc77f7bff5509cbf7fe935ede">XV_HdmiTx_DdcWrite()</a>.</p>

</div>
</div>
<a class="anchor" id="a1e7d988ba6707bb1cd58fa9af9db6ae0"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_CLK_DIV_MASK&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Clock Divider mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a3fe50d870f063d85a274d2cbe9dee549">XV_HdmiTx_DdcInit()</a>.</p>

</div>
</div>
<a class="anchor" id="a0183fc18bbe56540d95fc291e3060c38"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a0b2d0351f601ac8afdc99e651a916111"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="afaed19df9105685cea7b51363e5aab38"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a3fe50d870f063d85a274d2cbe9dee549">XV_HdmiTx_DdcInit()</a>, <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, and <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>.</p>

</div>
</div>
<a class="anchor" id="a25f1a215971c5370677b19e3b9f16bf2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Run mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, and <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>.</p>

</div>
</div>
<a class="anchor" id="aab4ea6581cb2fd09a5aabd906da25b17"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="aafc52187f15507e2b6b6f7438ddb3c8c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_DAT_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Data Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>.</p>

</div>
</div>
<a class="anchor" id="a4af3a11ac2e2a2190f6e8c39111199d3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="af77c4ab50461a2356e62aaa8fa279bab"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_ACK_MASK&#160;&#160;&#160;(1&lt;&lt;5)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status ACK mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#abdb511167dc499eacf28789225e83a24">XV_HdmiTx_DdcGetAck()</a>.</p>

</div>
</div>
<a class="anchor" id="ad2f3f71a213bc05457101200b03d2ebe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_BUSY_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

</div>
</div>
<a class="anchor" id="a108fb0a980dd01604d286d675f001a21"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_CMD_FULL&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo full. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>.</p>

</div>
</div>
<a class="anchor" id="ab64afd200f27ec3c82835a75eca6f61c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_CMD_WRDS_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo words mask. </p>

</div>
</div>
<a class="anchor" id="a14e07ba89f7f88769f399f1e7fa640dc"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_CMD_WRDS_SHIFT&#160;&#160;&#160;16</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Command fifo words shift. </p>

</div>
</div>
<a class="anchor" id="ab39f53e62517e7756ccaae1972635e71"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DAT_EMPTY&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data fifo empty. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>.</p>

</div>
</div>
<a class="anchor" id="a453c5f4507cb2b4d399eb0f778ccf934"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DAT_WRDS_MASK&#160;&#160;&#160;0xFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data fifo words mask. </p>

</div>
</div>
<a class="anchor" id="a59938ef823d937157bdbe0ffd06ed0d8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DAT_WRDS_SHIFT&#160;&#160;&#160;24</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Data fifo words shift. </p>

</div>
</div>
<a class="anchor" id="a5c2fcc8362b12929e9069f044c452bd7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_DONE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Busy mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>.</p>

</div>
</div>
<a class="anchor" id="ad944d773e9619b1d2076aa5bc0d9f4e2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Event mask. </p>

</div>
</div>
<a class="anchor" id="aed853aca89756ea743e083e7573d1617"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status IRQ mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="add689faff8e7c346c9d8202355678a22"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_DDC_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#abdb511167dc499eacf28789225e83a24">XV_HdmiTx_DdcGetAck()</a>, <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>, and <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="ab98e29e866183af70534dbf21deb4963"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_SCL_MASK&#160;&#160;&#160;(1&lt;&lt;6)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC State of SCL Input mask. </p>

</div>
</div>
<a class="anchor" id="ae486edb257d9135145951631a6b4b110"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_SDA_MASK&#160;&#160;&#160;(1&lt;&lt;7)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC State of SDA Input mask. </p>

</div>
</div>
<a class="anchor" id="ab4cc4517f9d2cdacd81718603c6a2308"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_DDC_STA_TIMEOUT_MASK&#160;&#160;&#160;(1&lt;&lt;4)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>DDC Status Timeout mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>.</p>

</div>
</div>
<a class="anchor" id="a156f0cd891a36ae3a64beec049eec7e2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_HPD_TIMEGRID_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(13*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO HPD Config. </p>
<ul>
<li>offset </li>
</ul>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a0711485d228f909cc65b275f866e526c"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_HW_H_</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Prevent circular inclusions by using protection macros. </p>

</div>
</div>
<a class="anchor" id="a90f7af607960cdf44deb2b43aab27254"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx_In32&#160;&#160;&#160;Xil_In32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Input Operations. </p>

</div>
</div>
<a class="anchor" id="a74530507b4700c300feb4eceed05668f"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_16&#160;&#160;&#160;0xFFFF</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>16 bit mask value </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a9647e1e833bcf466af722bb35001ab8e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_BLUE_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Blue Component Register * offset. </p>

</div>
</div>
<a class="anchor" id="a3639d48e4561aad19842fd0d94a845a2"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="ad38ac97d5502d061626fe17deb93b658"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_CTRL_NOISE_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Noise. </p>

</div>
</div>
<a class="anchor" id="aa07be6429aa3de9196a5772fb5fb9df1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Register * offset. </p>

</div>
</div>
<a class="anchor" id="a4a2e6183da180f5788efe86b724434b8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Run mask. </p>

</div>
</div>
<a class="anchor" id="ae10fec02c7d56b2f48deee7af38a7b8e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="aca10d7d68e20ce01b1cf316e595f36aa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_GREEN_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Green Component Register * offset. </p>

</div>
</div>
<a class="anchor" id="a420855708f2f362229d89e1bac673151"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Identification * Register offset. </p>

</div>
</div>
<a class="anchor" id="a348a93aa41e2334b3daa3cdd15e4b8a7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_RED_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Red Component Register * offset. </p>

</div>
</div>
<a class="anchor" id="aab51c879f7c90771a1d8e0ad70a4c012"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_MASK_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_MASK_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>MASK Status Register * offset. </p>

</div>
</div>
<a class="anchor" id="a6038ccff274de8b99efc34332d0c41d9"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx_Out32&#160;&#160;&#160;Xil_Out32</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Output Operations. </p>

</div>
</div>
<a class="anchor" id="ad1d5bdab7fa4daf868d93d2edd96f566"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(3*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Clear * offset. </p>

</div>
</div>
<a class="anchor" id="a912027acfdcf62f09ebcb9c4eafb1a74"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_IE_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Interrupt Enable mask. </p>

</div>
</div>
<a class="anchor" id="a09b04c19ceb81d2b9e5064d53e232e17"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(1*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register * offset. </p>

</div>
</div>
<a class="anchor" id="a40a412194d70fcbb53cef17eea048fa3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_RUN_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Run mask. </p>

</div>
</div>
<a class="anchor" id="a8e98120a6a24452d2865d24f740129b1"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_CTRL_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(2*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Control Register Set * offset. </p>

</div>
</div>
<a class="anchor" id="a5131cd2488ca4a797d71849293cc1109"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_ID&#160;&#160;&#160;0x2200</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>TX's PIO ID. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="a0f3575afd1ca4f63ffa6c725ff78ee7d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_ID_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(0*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Identification * Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

</div>
</div>
<a class="anchor" id="af0d1a093d1b0ef6ff6d0c595fbbc689d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_BRDG_LOCKED_MASK&#160;&#160;&#160;(1&lt;&lt;9)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Bridge Locked mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a183040712bab60e3b122ced003b6094d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_BRDG_OVERFLOW_MASK&#160;&#160;&#160;(1&lt;&lt;10)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Bridge Overflow mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="aeeca103fdb0a14d806a07cbbbac3a5a6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_BRDG_UNDERFLOW_MASK&#160;&#160;&#160;(1&lt;&lt;11)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Bridge Underflow mask. </p>
<p>DDC (Display Data Channel) peripheral register offsets The DDC is the second peripheral on the local bus </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ab26c31b92aedb7564284403ca2db65f5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_EVT_FE_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(12*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Falling Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a5393d399e287df6c50b6c32b90b1cf93"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_EVT_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(10*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Register * offset. </p>

</div>
</div>
<a class="anchor" id="a50a497ec4e91768009efd7752e7ed9f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_EVT_RE_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(11*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Event Rising Edge Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a38b7234925ae25a8a5104c446e2b0c50"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_HPD_MASK&#160;&#160;&#160;(1&lt;&lt;2)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In HPD mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a02fe47969aef0025a0dcde5f67059f4a"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_HPD_TOGGLE_MASK&#160;&#160;&#160;(1&lt;&lt;8)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In HPD toggle mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="af84ed4e0a3e63ee5b5eeb18b5f9172f6"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_LNK_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In link ready mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="ae1aa781005ce21dab9e7af6e4c091d0e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(9*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Register offset. </p>

</div>
</div>
<a class="anchor" id="afe3ba46026108ca4004a2c1f4e175cda"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_PPP_MASK&#160;&#160;&#160;0x07</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Pixel packing phase mask. </p>

</div>
</div>
<a class="anchor" id="a53a26ad8c741bb6defdabaf539c15f76"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_PPP_SHIFT&#160;&#160;&#160;5</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Pixel packing phase shift. </p>

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<a class="anchor" id="a8eae374abecb5156f5827c2543467866"></a>
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          <td class="memname">#define XV_HDMITX_PIO_IN_VID_RDY_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In video ready mask. </p>

</div>
</div>
<a class="anchor" id="a5e6881f3d1d651347a8e507c6d708aa6"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_IN_VS_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO In Vsync mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

</div>
</div>
<a class="anchor" id="a43259fa8be8e6d4990e225e7ef66deb6"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_BRIDGE_PIXEL_MASK&#160;&#160;&#160;(1&lt;&lt;30)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_Pixel repeat mask. </p>

</div>
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<a class="anchor" id="ae631917853f4efc05ec48b91a487e22e"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_BRIDGE_YUV420_MASK&#160;&#160;&#160;(1&lt;&lt;29)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Bridge_YUV420 mask. </p>

</div>
</div>
<a class="anchor" id="a57cd09ceda16cfc89ad51ab5fd16c625"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_CLR_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(7*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Clear * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a0e8e1d49d9f1cbcf266b5780a7724dab">XV_HdmiTx_ClearGcpAvmuteBit()</a>, <a class="el" href="xv__hdmitx_8h.html#af0f79865b06ffc79b2e92f1023dc2652">XV_HdmiTx_ClearGcpClearAvmuteBit()</a>, <a class="el" href="xv__hdmitx_8h.html#a80f9f6414491351d34827b3c5e7f717a">XV_HdmiTx_EXT_SYSRST()</a>, <a class="el" href="xv__hdmitx_8h.html#aefad89689cab1a7ddcc37873b08a8faa">XV_HdmiTx_EXT_VRST()</a>, <a class="el" href="xv__hdmitx_8h.html#a44187420a93cd54ee4b68db1e80cd1e1">XV_HdmiTx_INT_LRST()</a>, and <a class="el" href="xv__hdmitx_8h.html#a7df3873e5e622d92c651adbef0b83b0e">XV_HdmiTx_INT_VRST()</a>.</p>

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<a class="anchor" id="a564d1abff6cb04057811a461cfbcb692"></a>
<div class="memitem">
<div class="memproto">
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          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_MASK&#160;&#160;&#160;0x30</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Depth mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>.</p>

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</div>
<a class="anchor" id="aa3936d875363ae229e89ab0d93005173"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_DEPTH_SHIFT&#160;&#160;&#160;4</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Depth shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>.</p>

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</div>
<a class="anchor" id="a461cc5f1205b18c92863bbd3042540b7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_SPACE_MASK&#160;&#160;&#160;0xC00</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>.</p>

</div>
</div>
<a class="anchor" id="ac01a89ba24d5a2044caa1377a5aea7aa"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_COLOR_SPACE_SHIFT&#160;&#160;&#160;10</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Color Space shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>.</p>

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</div>
<a class="anchor" id="ae6f495059257675ab6aab20debbb29ae"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_EXT_SYSRST_MASK&#160;&#160;&#160;(1&lt;&lt;22)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_SYSRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a80f9f6414491351d34827b3c5e7f717a">XV_HdmiTx_EXT_SYSRST()</a>.</p>

</div>
</div>
<a class="anchor" id="a85c45b96a6535758a64f4bbde6736b30"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_EXT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;21)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out EXT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#aefad89689cab1a7ddcc37873b08a8faa">XV_HdmiTx_EXT_VRST()</a>.</p>

</div>
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<a class="anchor" id="aecae9177f56bf35251db6c967b60c2a3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_GCP_AVMUTE_MASK&#160;&#160;&#160;(1&lt;&lt;31)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out GCP_AVMUTE mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a0e8e1d49d9f1cbcf266b5780a7724dab">XV_HdmiTx_ClearGcpAvmuteBit()</a>, and <a class="el" href="xv__hdmitx_8h.html#a495a1c638020f63a0f9b30cf9584c57e">XV_HdmiTx_SetGcpAvmuteBit()</a>.</p>

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</div>
<a class="anchor" id="a5057e256f62c3af0dc0c4e08a6ebf5b3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_GCP_CLEARAVMUTE_MASK&#160;&#160;&#160;(1&lt;&lt;28)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out GCP_CLEARAVMUTE mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#af0f79865b06ffc79b2e92f1023dc2652">XV_HdmiTx_ClearGcpClearAvmuteBit()</a>, and <a class="el" href="xv__hdmitx_8h.html#a9f140138d5c101dcdf267acf1645f9ac">XV_HdmiTx_SetGcpClearAvmuteBit()</a>.</p>

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<a class="anchor" id="a190850cf65d40a36c67965b58ab719a7"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_INT_LRST_MASK&#160;&#160;&#160;(1&lt;&lt;20)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_LRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a44187420a93cd54ee4b68db1e80cd1e1">XV_HdmiTx_INT_LRST()</a>.</p>

</div>
</div>
<a class="anchor" id="aaae3285766545ae8b717a709c376d449"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_INT_VRST_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out INT_VRST mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a7df3873e5e622d92c651adbef0b83b0e">XV_HdmiTx_INT_VRST()</a>.</p>

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</div>
<a class="anchor" id="a8b22105cf60c90514691a778c3652769"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_MODE_MASK&#160;&#160;&#160;(1&lt;&lt;3)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Mode mask. </p>

</div>
</div>
<a class="anchor" id="a3aec0a8a571c50309c582ac0a3a66cda"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_MSK_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(8*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Mask Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>, <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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</div>
<a class="anchor" id="a73655a77916a05b7d8f82a921f15f7be"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(5*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>, <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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</div>
<a class="anchor" id="a92829fb1e590c09d7cb030093ed38ba3"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_PIXEL_RATE_MASK&#160;&#160;&#160;0xC0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>.</p>

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</div>
<a class="anchor" id="ad507e1024a352cdf174c99ade627b5fb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_PIXEL_RATE_SHIFT&#160;&#160;&#160;6</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Pixel Rate shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>.</p>

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</div>
<a class="anchor" id="a3492813bb70421de0a228014bf8d949b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_RST_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Reset mask. </p>

</div>
</div>
<a class="anchor" id="ad69a761dfc73ee26434f08f27c83dcdf"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_MASK&#160;&#160;&#160;0x300</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

</div>
</div>
<a class="anchor" id="ae81b504f82f4bb53a7f6340c91b722f5"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SAMPLE_RATE_SHIFT&#160;&#160;&#160;8</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Sample Rate shift. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

</div>
</div>
<a class="anchor" id="aec658e14a00798e20cec912c330c4d0d"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SCRM_MASK&#160;&#160;&#160;(1&lt;&lt;12)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Scrambler mask. </p>

</div>
</div>
<a class="anchor" id="afb3e424d18e1c4b146232b67699824eb"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_OUT_SET_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(6*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Out Register Set * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#a80f9f6414491351d34827b3c5e7f717a">XV_HdmiTx_EXT_SYSRST()</a>, <a class="el" href="xv__hdmitx_8h.html#aefad89689cab1a7ddcc37873b08a8faa">XV_HdmiTx_EXT_VRST()</a>, <a class="el" href="xv__hdmitx_8h.html#a44187420a93cd54ee4b68db1e80cd1e1">XV_HdmiTx_INT_LRST()</a>, <a class="el" href="xv__hdmitx_8h.html#a7df3873e5e622d92c651adbef0b83b0e">XV_HdmiTx_INT_VRST()</a>, <a class="el" href="xv__hdmitx_8h.html#a495a1c638020f63a0f9b30cf9584c57e">XV_HdmiTx_SetGcpAvmuteBit()</a>, and <a class="el" href="xv__hdmitx_8h.html#a9f140138d5c101dcdf267acf1645f9ac">XV_HdmiTx_SetGcpClearAvmuteBit()</a>.</p>

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<a class="anchor" id="aca60ad2b7145ae20f665c42136e63bb7"></a>
<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define XV_HDMITX_PIO_STA_EVT_MASK&#160;&#160;&#160;(1&lt;&lt;1)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Event mask. </p>

</div>
</div>
<a class="anchor" id="aa8c178b5851211ca5b20faee275a73f8"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_STA_IRQ_MASK&#160;&#160;&#160;(1&lt;&lt;0)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Interrupt mask. </p>

<p>Referenced by <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

</div>
</div>
<a class="anchor" id="a9374a3f25d4d9c91c02d383d66443b4b"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HDMITX_PIO_STA_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(4*4))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>PIO Status Register * offset. </p>

<p>Referenced by <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>.</p>

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</div>
<a class="anchor" id="a41b837de9bdbba60a15baa46362dd851"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define XV_HdmiTx_ReadReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a90f7af607960cdf44deb2b43aab27254">XV_HdmiTx_In32</a>((BaseAddress) + (RegOffset))</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>This macro reads a value from a HDMI TX register. </p>
<p>A 32 bit read is performed. If the component is implemented in a smaller width, only the least significant data is read from the register. The most significant data will be read as 0.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file).</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>The 32-bit value of the register.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: u32 <a class="el" href="xv__hdmitx__hw_8h.html#a41b837de9bdbba60a15baa46362dd851" title="This macro reads a value from a HDMI TX register. ">XV_HdmiTx_ReadReg(UINTPTR BaseAddress, u32 RegOffset)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#ae75f2ab194a44b9f67b7fa9d4545cb57">XV_HdmiTx_AuxSend()</a>, <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>, <a class="el" href="xv__hdmitx_8c.html#abdb511167dc499eacf28789225e83a24">XV_HdmiTx_DdcGetAck()</a>, <a class="el" href="xv__hdmitx_8c.html#a8c78e41a57fd48c1a392bc7448b93488">XV_HdmiTx_DdcReadData()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx_8h.html#a1969dd5561dba784fdb82a4b8e634256">XV_HdmiTx_GetAudioFormat()</a>, <a class="el" href="xv__hdmitx__intr_8c.html#a25e91176ce93f223449dcb56c375ac51">XV_HdmiTx_IntrHandler()</a>, <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>, <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>, and <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>.</p>

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          <td class="memname">#define XV_HDMITX_SHIFT_16&#160;&#160;&#160;16</td>
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<p>16 shift value </p>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>, and <a class="el" href="xv__hdmitx__selftest_8c.html#a0934e75073446925a9698485b52e2c00">XV_HdmiTx_SelfTest()</a>.</p>

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          <td class="memname">#define XV_HDMITX_TOGGLE_CONF_OFFSET&#160;&#160;&#160;((XV_HDMITX_PIO_BASE)+(14*4))</td>
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<p>PIO HPD Config. </p>
<ul>
<li>Register offset </li>
</ul>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>.</p>

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          <td class="memname">#define XV_HDMITX_VER_BASE&#160;&#160;&#160;(0*64)</td>
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<p>&lt; VER (Version Interface) peripheral register offsets </p>
<p>&lt; The VER is the first peripheral on the local bus </p>

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          <td class="memname">#define XV_HDMITX_VER_ID_OFFSET&#160;&#160;&#160;((<a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>)+(0*4))</td>
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<p>VER Identification * Register offset. </p>

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          <td class="memname">#define XV_HDMITX_VER_VERSION_OFFSET&#160;&#160;&#160;((<a class="el" href="xv__hdmitx__hw_8h.html#a3eafe27fd10317ecb42fe689ca593212">XV_HDMITX_VER_BASE</a>)+(1*4))</td>
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<p>VER Version Register * offset. </p>
<p>PIO (Parallel Interface) peripheral register offsets The PIO is the first peripheral on the local bus </p>

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          <td class="memname">#define XV_HdmiTx_WriteReg</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">BaseAddress, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">RegOffset, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">Data&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td>&#160;&#160;&#160;<a class="el" href="xv__hdmitx__hw_8h.html#a6038ccff274de8b99efc34332d0c41d9">XV_HdmiTx_Out32</a>((BaseAddress) + (RegOffset), (u32)(Data))</td>
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<p>This macro writes a value to a HDMI TX register. </p>
<p>A 32 bit write is performed. If the component is implemented in a smaller width, only the least significant data is written.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">BaseAddress</td><td>is the base address of the HDMI TX core instance. </td></tr>
    <tr><td class="paramname">RegOffset</td><td>is the register offset of the register (defined at the top of this file) to be written. </td></tr>
    <tr><td class="paramname">Data</td><td>is the 32-bit value to write into the register.</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>None.</dd></dl>
<dl class="section note"><dt>Note</dt><dd>C-style signature: void <a class="el" href="xv__hdmitx__hw_8h.html#a3b74e3c052543284012c23ec717af9d1" title="This macro writes a value to a HDMI TX register. ">XV_HdmiTx_WriteReg(UINTPTR BaseAddress, u32 RegOffset, u32 Data)</a> </dd></dl>

<p>Referenced by <a class="el" href="xv__hdmitx_8h.html#ae75f2ab194a44b9f67b7fa9d4545cb57">XV_HdmiTx_AuxSend()</a>, <a class="el" href="xv__hdmitx_8h.html#acfeb8c295991a88031817404dd4135f3">XV_HdmiTx_CfgInitialize()</a>, <a class="el" href="xv__hdmitx_8h.html#a0e8e1d49d9f1cbcf266b5780a7724dab">XV_HdmiTx_ClearGcpAvmuteBit()</a>, <a class="el" href="xv__hdmitx_8h.html#af0f79865b06ffc79b2e92f1023dc2652">XV_HdmiTx_ClearGcpClearAvmuteBit()</a>, <a class="el" href="xv__hdmitx_8h.html#a3fe50d870f063d85a274d2cbe9dee549">XV_HdmiTx_DdcInit()</a>, <a class="el" href="xv__hdmitx_8c.html#ace17bdbb13a83051c81e70162707c1bb">XV_HdmiTx_DdcWaitForDone()</a>, <a class="el" href="xv__hdmitx_8c.html#a4e0fa58d0c4b103aaa0493f875b7a8fb">XV_HdmiTx_DdcWriteCommand()</a>, <a class="el" href="xv__hdmitx_8h.html#a80f9f6414491351d34827b3c5e7f717a">XV_HdmiTx_EXT_SYSRST()</a>, <a class="el" href="xv__hdmitx_8h.html#aefad89689cab1a7ddcc37873b08a8faa">XV_HdmiTx_EXT_VRST()</a>, <a class="el" href="xv__hdmitx_8h.html#a44187420a93cd54ee4b68db1e80cd1e1">XV_HdmiTx_INT_LRST()</a>, <a class="el" href="xv__hdmitx_8h.html#a7df3873e5e622d92c651adbef0b83b0e">XV_HdmiTx_INT_VRST()</a>, <a class="el" href="xv__hdmitx_8h.html#a32872739c2a5ea02cf92aadc79aa385f">XV_HdmiTx_SetAudioChannels()</a>, <a class="el" href="xv__hdmitx_8h.html#ad2d696a57ba6d62205853f83b4fdc589">XV_HdmiTx_SetAudioFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#a9271b92c3193e1ce46a2b610080c6f06">XV_HdmiTx_SetColorDepth()</a>, <a class="el" href="xv__hdmitx_8h.html#aa8eb6378fdb4a48a22fdedb89cc3702a">XV_HdmiTx_SetColorFormat()</a>, <a class="el" href="xv__hdmitx_8h.html#a495a1c638020f63a0f9b30cf9584c57e">XV_HdmiTx_SetGcpAvmuteBit()</a>, <a class="el" href="xv__hdmitx_8h.html#a9f140138d5c101dcdf267acf1645f9ac">XV_HdmiTx_SetGcpClearAvmuteBit()</a>, <a class="el" href="xv__hdmitx_8h.html#abe6e4feed643a46f8c5a09494d2e2874">XV_HdmiTx_SetPixelRate()</a>, and <a class="el" href="xv__hdmitx_8h.html#abb0cde0fed5637779f430ca6eb2a9199">XV_HdmiTx_SetSampleRate()</a>.</p>

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